1. Field of the Invention
This invention relates to computer circuitry and, more particularly, to methods and apparatus for arbitrating an interface in the addressing circuitry of a microprocessor.
2. History of the Prior Art
The 80486 microprocessor manufactured by Intel Corporation, Santa Clara, Calif., provides architecture which allows addressing in both segmentation and paging modes. In order to accomplish this, a segmentation unit is provided for generating thirty-two bit linear addresses used in segmentation addressing. These linear addresses are transferred to the paging unit where they are translated by means of page look-up tables to page addresses if paging is enabled. If paging is not enabled, the linear addresses generated by the segmentation unit are simply transferred through the paging unit and utilized without change as the physical addresses for accessing information in memory. Details of the addressing arrangement of the microprocessor are provided in a publication entitled i486, published by Intel Corporation, August 1989.
The microprocessor pipelines instructions for execution and utilizes a prefetch unit to assist with the pipelining. Linear addresses are also provided by the prefetch unit for accessing information. The linear addresses provided by the prefetch unit can also optionally be page relocated. In order not to have to duplicate the paging unit, addresses generated by both the segmentation unit and the prefetch unit are sent to the same paging unit. Since both of the segmentation unit and the prefetch unit may want to provide addresses at the same time, it is necessary to provide an arrangement for arbitrating the use of the linear address bus which is the input path to the paging unit.